SOICs are originally developed for reflow soldering. In the late 80's of the last century tests were done on 1.27 mm pitch SOICs, to find layout rules for wavesoldering such components with a chipwave. The reason was a commercial one. The suppliers of such components supported and promoted any application in order to sell more of these components. Therefore they provided layout rules for wave soldering; using extra pads at the drainage edge of the component in order to collect the solder that otherwise could give bridge formation on the last joints.
The tests that were done to provide these design rules were made on PCBs, on which only these components were mounted. So no other components such as SMD capacitors or resistors, or other joints were adjacent to these SOICs. During these tests the optimal pad size for such components were found and these dimensions were published as the design rules for wave soldering.
Please note that these pad dimensions and the use of the extra drainage pads are different of the design rules for reflow soldering! If only one set of design rules are given, they are for reflow soldering only. Never use the reflow design rules for wave soldering applications. The outcome in solderbridging will often be disastrous.